1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same. More particularly, the present invention relates to a semiconductor device which avoids a degradation in contact resistance due to annealing steps in the fabrication process and a method of fabricating the same.
2. Description of the Related Art
In a p-channel MOS transistor having a p.sup.+ -type polycrystalline silicon (hereinafter called polysilicon) gate electrode, the short channel effect can be further reduced and a lower threshold voltage (V.sub.th) of the MOS transistor can be set, as compared with a p-channel MOS transistor having an n.sup.+ -type polysilicon gate electrode. This is disclosed, for example, in IEEE, IEDM, Technical Digest, pp. 418-422 (1984).
In order to electrically connect a p.sup.+ -type impurity diffused region which is formed in a semiconductor substrate with a polysilicon interconnection, a p.sup.+ -type polysilicon film is used as the polysilicon interconnection. The p.sup.+ -type polysilicon film has a higher specific resistance than those of typical metals. Since an interconnection and an electrode are preferably formed from a material having a low specific resistance, the interconnection and the electrode are sometimes formed of a p.sup.+ -type polycide film in which a refractory metal silicide film or the like is laminated on the p.sup.+ -type polysilicon film.
The p.sup.+ -type polycide film is made from refractory materials which will not deteriorate even by an annealing process at a temperature of 900.degree. C. or higher. Therefore, it is possible to form a borophospho silicate glass (BPSG) film as an interlevel insulating film after the formation of the interconnection and the electrode from the p.sup.+ -type polycide film, and to anneal the BPSG film for planarization. A semiconductor device which is fabricated in such a manner is shown in Japanese Laid-Open Patent Publication No. 57-192079.
Even when the BPSG film is not used as the interlevel insulating film, it is necessary to perform annealing after the formation of the p.sup.+ -type polycide film, in order to activate the p.sup.+ -type impurities. During the annealing, the boron concentration may decrease due to an outdiffusion of boron. In order to prevent the decrease in boron concentration, it is required to deposit an insulating film on the p.sup.+ -type polycide film prior to the annealing. This is disclosed, for example, in J. Vac. Sci. Technol. B, vol. 5, pp. 1674-1688, 1987.
However, the above prior art has the following problem.
There is a known phenomenon that, when the p.sup.+ -type polycide film is annealed, boron will segregate to the interface between the p.sup.+ -type polycide film and the insulating film covering the p.sup.+ -type polycide film, whereby the boron concentration in the p.sup.+ -type polycide film decreases. This phenomenon is described, for example, in IEEE, IEDM, Technical Digest, pp. 407-410 (1985).
The decrease in boron concentration will cause the following problems: (1) when the p.sup.+ -type polycide film is used as a gate electrode of an MOS transistor, the threshold voltage of the MOS transistor will vary with the decrease in boron concentration; and (2) when the p.sup.+ -type polycide film is used as an interconnection which is in contact with a p-type impurity diffused region, a contact resistance will increase with the decrease in boron concentration.